1. Technical Field
The present application relates, in general, to phase locked loops.
2. Description of the Related Art
Phase locked loops are electrical circuits which provide relatively stable output waveforms of varying frequencies by use of a master oscillating circuit that has a relatively fixed frequency.
FIG. 1 shows a block diagram representation of a phase locked loop 150. The master oscillator 100 has a voltage input labeled UM. The master oscillator 100 produces highly stable oscillation about some defined center frequency of the oscillator. The frequency of oscillation can be varied slightly by varying the value of voltage input UM. The master oscillator 100 has a sensitivity rating of KM Hertz per volt (Hz/Volt) which indicates the proportionality between the input voltage and the frequency of oscillation of the output voltage of the master oscillator 100.
A slave VCO 102 produces an oscillatory output signal whose frequency is dependent upon the value of a voltage input VVCO of the slave VCO 102. The slave VCO 102 generally has a sensitivity rating of KV Hertz per volt (Hz/Volt) which indicates the proportionality between the input voltage and the frequency of oscillation of the output voltage of the slave VCO 102.
The master oscillator 100 typically oscillates in a highly stable manner, but is relatively limited with respect to the frequencies at which it may oscillate. In contrast, the slave VCO 102 is typically highly flexible with respect to the frequencies at which it may oscillate, but oscillates in a highly unstable manner. The phase locked loop 150 is a circuit which attempts to take advantage of the best properties of the master oscillator 100 and the slave VCO 102, while avoiding the limitations of both.
The output of the phase locked loop 150, which is also the output of the slave VCO 102, is fed to a “divide by N” (1/N) frequency divider 104. The “divide by N” frequency divider 104 accepts as input a voltage waveform having a frequency of f1 and transmits as output a “divided by N” frequency version of the f1 frequency waveform. The output of the 1/N frequency divider 104 is fed into one input of a differential frequency/phase voltage controller 106. The output of master oscillator 100 is fed into another input of the differential frequency/phase voltage controller 106.
Differential frequency/phase voltage controller 106 is shown as a summing junction in negative feedback configuration. This configuration indicates that the differential frequency/phase voltage controller 106 will produce substantially constant output (e.g., zero) if its two inputs are the same, but will produce some change in its output if its two inputs are different. For example, in the situation where the differential frequency/phase voltage controller 106 detects that the voltage waveform emerging from the 1/N frequency divider 104 is “lagging” the voltage waveform emerging from the master oscillator 100, the differential frequency/phase voltage controller 106 would slightly increase its output voltage to cause a corresponding increase of the output frequency of the waveform produced by the slave VCO 102. Conversely, in the situation where the differential frequency/phase voltage controller 106 detects that the voltage waveform emerging from the 1/N frequency divider 104 is “leading” the voltage waveform emerging from master oscillator 100, in one implementation the differential frequency/phase voltage controller 106 would slightly decrease its output voltage to cause a correspondent decrease of the output frequency of the waveform produced by the slave VCO 102.
Note that even though the differential frequency/phase voltage controller 106 is actually detecting a frequency differential, if the depicted frequency differential is viewed as being “relative to” the 100 kHz reference frequency produced by the master oscillator 100, from the standpoint of the differential frequency/phase voltage controller 106 it appears “as if” the output voltage of the {fraction (1/10)}frequency divider 104 is “out of phase” (e.g., either “lagging” or “leading” in time) with the 100 kHz reference frequency waveform. Consequently, those having ordinary skill in the art often refer to the differential frequency/phase detector portion (e.g., see FIG. 3) of the differential frequency/phase voltage controller 106 solely as a “phase detector.”
The one block which has not yet been discussed is a loop filter 108 block. As noted, the differential frequency/phase voltage controller 106 determines the difference in frequency/phase between its inputs, and outputs a voltage signal corresponding to the difference in more-or-less real time. As also noted, this output signal of the differential frequency/phase voltage controller 106 is ultimately used to drive the slave VCO 102. If the slave VCO 102 is allowed to respond to every real time voltage fluctuation of the differential frequency/phase voltage controller 106, the slave VCO 102 will often “overreact” and produce a relatively unstable output voltage waveform. Better stability is achieved by making the slave VCO 102 “less sensitive” to the more quickly varying changes of the voltage output of the differential frequency/phase voltage controller 106. This is achieved by placing the loop filter 108 between the differential frequency/phase voltage controller 106 and the voltage input VVCO, of the slave VCO 102, where a loop filter 108 screens, or “filters out,” any rapid changes in the output voltage of the differential frequency/phase voltage controller 106 which tend to make the output of the slave VCO 102 (and hence the output of the phase locked loop 150) behave erratically.
The inventor has recognized needs related to stability of related art phase locked loops, and has devised methods and systems to satisfy those needs. Because the inventor's recognition of such needs constitutes a part of the inventive content herein, such recognized needs are discussed in the following detailed description.